RiscV

Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) through superscalar and out-of-order (OoO) execution is crucial. However, high-performance open-source RISC-V cores face adoption challenges: some (e.g. BOOM, Xiangshan) are developed in Chisel with limited support from industrial electronic design automation (EDA) tools. Others, like the XuanTie C910 core, use proprietary interfaces and protocols, including non-standard AXI protocol extensions, interrupts, and debug support.

In this work, we present a modified version of the OoO C910 core to achieve full RISC-V standard compliance in its debug, interrupt, and memory interfaces. We also introduce CVA6S+, an enhanced version of the dual-issue, industry-supported open-source CVA6 core. CVA6S+ achieves 34.4% performance improvement over CVA6 core.

We conduct a detailed performance, area, power, and energy analysis on the superscalar out-of-order C910, superscalar in-order CVA6S+ and vanilla, single-issue in-order CVA6, all implemented in a 22nm technology and integrated into Cheshire, an open-source modular SoC. We examine the performance and efficiency of different microarchitectures using the same ISA, SoC, and implementation with identical technology, tools, and methodologies. The area and performance rankings of CVA6, CVA6S+, and C910 follow expected trends: compared to the scalar CVA6, CVA6S+ shows an area increase of 6% and an IPC improvement of 34.4%, while C910 exhibits a 75% increase in area and a 119.5% improvement in IPC. However, efficiency analysis reveals that CVA6S+ leads in area efficiency (GOPS/mm2), while the C910 is highly competitive in energy efficiency (GOPS/W). This challenges the common belief that high performance in superscalar and out-of-order cores inherently comes at a significant cost in area and energy efficiency.

The KDE Frameworks are a set of 83 add-on libraries for programming with Qt. Part of it is also the syntax highlighting engine, used not only by KDE applications like Kate and KDevelop; but also by some others like Qt Creator.

Version 6.14 of KDE Framworks add support for RISC-V instructions/registers/… in GNU Assembler. Including some vendor-specific instructions.

Quick introduction to the RISC-V Vector spec. I thought some people might find this useful if they're trying to learn what SEW, ELEN, VLMAX, LMUL etc. mean.

The RISC-V vector C intrinsics provide users interfaces in the C language level to directly leverage the RISC-V “V” extension (RISC-V “V” Vector Extension, n.d.) (also abbreviated as “RVV”), with assistance from the compiler in handling instruction scheduling and register allocation. The intrinsics also aim to free users from responsibility of maintaining the correct configuration settings for the vector instruction executions. This document uses the term “RVV” as an abbreviation for the RISC-V “V” extension. This document uses the term “the RVV specification” to indicate the RISC-V “V” extension specification.

Earlier this month Canonical announced Ubuntu Linux support for the Orange Pi RV2 as a low-cost RISC-V developer board. The Orange Pi RV2 with eight RISC-V cores and 8GB of RAM costs just around $64 USD. The price point and specs were interesting that I ordered one and have been running performance benchmarks on it since for seeing how capable this is as finally an interesting, low-cost and readily available RISC-V board.

direct YT link: https://www.youtube.com/watch?v=9s8hPmCZ0mk