this post was submitted on 31 Oct 2023
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Curious what financial benefit is there to making it have 25% less memory bandwidth?
Is it to drive consumers to a more expensive product?
I get they have 25% less bandwidth. But why?
Cost. You get more bandwidth by having more interconnect which takes up die space which means you get fewer per wafer and lower your yield. TSMCs N3 process is very expensive and is rumored to be dealing with yield issues as well.